add game&rawdata

This commit is contained in:
Vasily Petrov 2026-06-17 23:06:51 +03:00
parent 0133cd976c
commit 49b34b5546
45731 changed files with 709831 additions and 0 deletions

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//
// Generated by Microsoft (R) D3DX9 Shader Compiler 9.11.519.0000
//
// fxc /nologo /Tps_1_1 /Emain_ps_1_1 /Zpr /Fctest\p11_postprocess.ps
// postprocess.ps
//
//
// Parameters:
//
// float4 c_brightness;
// sampler2D s_base0;
// sampler2D s_base1;
// sampler2D s_noise;
//
//
// Registers:
//
// Name Reg Size
// ------------ ----- ----
// c_brightness c0 1
// s_base0 s0 1
// s_base1 s1 1
// s_noise s2 1
//
ps_1_1
def c1, 0, 0, 0, 1
tex t0
tex t1
tex t2
add_d2 r0.xyz, t0, t1
dp3 r1, r0, v1
mul r1.w, r1.w, 1-v1.w
mad r0.xyz, r0, v1.w, r1.w
mul_x2 r1.xyz, t2, r0
lrp r0.xyz, v0.w, r0, r1
mad_x2 r0.xyz, r0, v0, c0
+ mov r0.w, c1.w
// approximately 10 instruction slots used (3 texture, 7 arithmetic)

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//
// Generated by Microsoft (R) D3DX9 Shader Compiler 9.11.519.0000
//
// fxc /nologo /Tps_2_0 /Emain_ps_1_1 /Zpr /Fctest\p20_postprocess.ps
// postprocess.ps
//
//
// Parameters:
//
// float4 c_brightness;
// sampler2D s_base0;
// sampler2D s_base1;
// sampler2D s_noise;
//
//
// Registers:
//
// Name Reg Size
// ------------ ----- ----
// c_brightness c0 1
// s_base0 s0 1
// s_base1 s1 1
// s_noise s2 1
//
ps_2_0
def c1, 0.5, 2, 1, 0
dcl v0
dcl v1
dcl_pp t0.xy
dcl_pp t1.xy
dcl_pp t2.xy
dcl_2d s0
dcl_2d s1
dcl_2d s2
texld_pp r1, t0, s0
texld_pp r2, t1, s1
texld_pp r0, t2, s2
add_pp r1.xyz, r1, r2
mul_pp r2.xyz, r1, c1.x
dp3_pp r2.x, r2, v1
mad_pp r1.xyz, r1, c1.x, -r2.x
mad_pp r2.xyz, v1.w, r1, r2.x
mul_pp r1.xyz, r0, r2
mad_pp r0.xyz, c1.y, -r1, r2
add_pp r1.xyz, r1, r1
mad_pp r0.xyz, v0.w, r0, r1
mad_pp r0.xyz, r0, v0, c0
add_pp r0.xyz, r0, r0
mov r0.w, c1.z
mov_pp oC0, r0
// approximately 16 instruction slots used (3 texture, 13 arithmetic)

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//
// Generated by Microsoft (R) D3DX9 Shader Compiler 9.11.519.0000
//
// fxc /nologo /Tps_3_0 /Emain_ps_1_1 /Zpr /Fctest\p30_postprocess.ps
// postprocess.ps
//
//
// Parameters:
//
// float4 c_brightness;
// sampler2D s_base0;
// sampler2D s_base1;
// sampler2D s_noise;
//
//
// Registers:
//
// Name Reg Size
// ------------ ----- ----
// c_brightness c0 1
// s_base0 s0 1
// s_base1 s1 1
// s_noise s2 1
//
ps_3_0
def c1, 0.5, 2, 1, 0
dcl_color_pp v0
dcl_color1_pp v1
dcl_texcoord_pp v2.xy
dcl_texcoord1_pp v3.xy
dcl_texcoord2_pp v4.xy
dcl_2d s0
dcl_2d s1
dcl_2d s2
texld_pp r0, v2, s0
texld_pp r1, v3, s1
add_pp r0.xyz, r0, r1
mul_pp r1.xyz, r0, c1.x
dp3_pp r0.w, r1, v1
mad_pp r0.xyz, r0, c1.x, -r0.w
mad_pp r2.xyz, v1.w, r0, r0.w
texld_pp r0, v4, s2
mul_pp r1.xyz, r2, r0
mad_pp r0.xyz, c1.y, -r1, r2
add_pp r1.xyz, r1, r1
mad_pp r0.xyz, v0.w, r0, r1
mad_pp r0.xyz, r0, v0, c0
add_pp oC0.xyz, r0, r0
mov_pp oC0.w, c1.z
// approximately 15 instruction slots used (3 texture, 12 arithmetic)

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--------------------------------------------------------------------------------
Running performance on file test\p11_impl_dt.ps
-------------------- NV30 --------------------
Target: GeForceFX 5800 Ultra (NV30) :: Unified Compiler: v77.72
Cycles: 4 :: # R Registers: 2
Pixel throughput (assuming 1 cycle texture lookup) 500.00 MP/s
--------------------------------------------------------------------------------
Running performance on file test\p11_impl_dt.ps
-------------------- NV35 --------------------
Target: GeForceFX 5900 Ultra (NV35) :: Unified Compiler: v77.72
Cycles: 4 :: # R Registers: 2
Pixel throughput (assuming 1 cycle texture lookup) 450.00 MP/s
--------------------------------------------------------------------------------
Running performance on file test\p11_impl_dt.ps
-------------------- NV40 --------------------
Target: GeForce 6800 Ultra (NV40) :: Unified Compiler: v77.72
Cycles: 4.00 :: R Regs Used: 2 :: R Regs Max Index (0 based): 1
Pixel throughput (assuming 1 cycle texture lookup) 1.60 GP/s
--------------------------------------------------------------------------------
Running performance on file test\p11_impl_dt.ps
-------------------- G70 --------------------
Target: GeForce 7800 GTX (G70) :: Unified Compiler: v77.72
Cycles: 4.00 :: R Regs Used: 2 :: R Regs Max Index (0 based): 1
Pixel throughput (assuming 1 cycle texture lookup) 2.58 GP/s

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//
// Generated by Microsoft (R) D3DX9 Shader Compiler 9.06.168.0000
//
// fxc /nologo /Tvs_1_1 /Emain /Zpr /Fctest\v11_tree_s_dt.vs tree_s_dt.vs
//
//
// Parameters:
//
// float4 L_hemi_color;
// float3 L_sun_color;
// float3 L_sun_dir_w;
// float4 c_bias;
// float4 c_scale;
// float2 c_sun;
// float4 consts;
// float4 dt_params;
// float3 eye_position;
// float4 fog_plane;
// row_major float4x4 m_VP;
// row_major float3x4 m_xform;
//
//
// Registers:
//
// Name Reg Size
// ------------ ----- ----
// m_VP c0 4
// m_xform c4 3
// fog_plane c7 1
// L_sun_color c8 1
// L_sun_dir_w c9 1
// L_hemi_color c10 1
// eye_position c11 1
// dt_params c12 1
// consts c13 1
// c_bias c14 1
// c_scale c15 1
// c_sun c16 1
//
vs_1_1
def c17, 1, 2, -1, 0.5
def c18, 0.75, 0.25, 0, 0
dcl_position v0
dcl_normal v1
dcl_texcoord v2
mov r0.w, c17.x
dp4 r0.x, c4, v0
dp4 r0.y, c5, v0
dp4 r0.z, c6, v0
dp4 oFog, r0, c7
dp4 oPos.x, c0, r0
dp4 oPos.y, c1, r0
mad r2.xyz, c17.y, v1, c17.z
dp4 oPos.z, c2, r0
dp3 r1.x, c4, r2
dp3 r1.y, c5, r2
dp3 r1.z, c6, r2
dp4 oPos.w, c3, r0
dp3 r1.x, r1, -c9
add r2.xyz, r0, -c11
mad r0.w, r1.x, c18.x, c18.y
mul r1.xyz, r0.w, c8
mov r0, c15
mad r0, r0, v1.w, c14
mad r0.xyz, c10, r0.w, r0
dp3 r2.x, r2, r2
mad r1.w, v1.w, c16.x, c16.y
rsq r0.w, r2.x
mad oD0.xyz, r1, r1.w, r0
rcp r0.w, r0.w
mul r0.xy, v2, c13
mul r0.w, r0.w, c12.w
mul oT1.xy, r0, c12
mul r0.w, r0.w, r0.w
mov oT0.xy, r0
min r0.w, r0.w, c17.x
add oD0.w, -r0.w, c17.x
mul oD1, r0.w, c17.w
// approximately 33 instruction slots used

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//
// Generated by Microsoft (R) D3DX9 Shader Compiler 9.06.168.0000
//
// fxc /nologo /Tvs_2_0 /Emain /Zpr /Fctest\v20_tree_s_dt.vs tree_s_dt.vs
//
//
// Parameters:
//
// float4 L_hemi_color;
// float3 L_sun_color;
// float3 L_sun_dir_w;
// float4 c_bias;
// float4 c_scale;
// float2 c_sun;
// float4 consts;
// float4 dt_params;
// float3 eye_position;
// float4 fog_plane;
// row_major float4x4 m_VP;
// row_major float3x4 m_xform;
//
//
// Registers:
//
// Name Reg Size
// ------------ ----- ----
// m_VP c0 4
// m_xform c4 3
// fog_plane c7 1
// L_sun_color c8 1
// L_sun_dir_w c9 1
// L_hemi_color c10 1
// eye_position c11 1
// dt_params c12 1
// consts c13 1
// c_bias c14 1
// c_scale c15 1
// c_sun c16 1
//
vs_2_0
def c17, 1, 2, -1, 0.5
def c18, 0.75, 0.25, 0, 0
dcl_position v0
dcl_normal v1
dcl_texcoord v2
mov r0.w, c17.x
dp4 r0.x, c4, v0
dp4 r0.y, c5, v0
dp4 r0.z, c6, v0
dp4 oFog, r0, c7
dp4 oPos.x, c0, r0
dp4 oPos.y, c1, r0
mad r2.xyz, c17.y, v1, c17.z
dp4 oPos.z, c2, r0
dp3 r1.x, c4, r2
dp3 r1.y, c5, r2
dp3 r1.z, c6, r2
dp4 oPos.w, c3, r0
dp3 r1.x, r1, -c9
add r2.xyz, r0, -c11
mad r0.w, r1.x, c18.x, c18.y
mul r1.xyz, r0.w, c8
mov r0, c15
mad r0, r0, v1.w, c14
mad r0.xyz, c10, r0.w, r0
dp3 r2.x, r2, r2
mad r1.w, v1.w, c16.x, c16.y
rsq r0.w, r2.x
mad oD0.xyz, r1, r1.w, r0
rcp r0.w, r0.w
mul r0.xy, v2, c13
mul r0.w, r0.w, c12.w
mul oT1.xy, r0, c12
mul r0.w, r0.w, r0.w
mov oT0.xy, r0
min r0.w, r0.w, c17.x
add oD0.w, -r0.w, c17.x
mul oD1, r0.w, c17.w
// approximately 33 instruction slots used

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//
// Generated by Microsoft (R) D3DX9 Shader Compiler 9.06.168.0000
//
// fxc /nologo /Tvs_3_0 /Emain /Zpr /Fctest\v30_tree_s_dt.vs tree_s_dt.vs
//
//
// Parameters:
//
// float4 L_hemi_color;
// float3 L_sun_color;
// float3 L_sun_dir_w;
// float4 c_bias;
// float4 c_scale;
// float2 c_sun;
// float4 consts;
// float4 dt_params;
// float3 eye_position;
// float4 fog_plane;
// row_major float4x4 m_VP;
// row_major float3x4 m_xform;
//
//
// Registers:
//
// Name Reg Size
// ------------ ----- ----
// m_VP c0 4
// m_xform c4 3
// fog_plane c7 1
// L_sun_color c8 1
// L_sun_dir_w c9 1
// L_hemi_color c10 1
// eye_position c11 1
// dt_params c12 1
// consts c13 1
// c_bias c14 1
// c_scale c15 1
// c_sun c16 1
//
vs_3_0
def c17, 1, 2, -1, 0.5
def c18, 0.75, 0.25, 0, 0
dcl_position v0
dcl_normal v1
dcl_texcoord v2
dcl_position o0
dcl_color o1
dcl_color1 o2
dcl_texcoord o3.xy
dcl_texcoord1 o4.xy
dcl_fog o5.x
mov r0.w, c17.x
dp4 r0.x, c4, v0
dp4 r0.y, c5, v0
dp4 r0.z, c6, v0
dp4 o5.x, r0, c7
dp4 o0.x, c0, r0
dp4 o0.y, c1, r0
mad r2.xyz, c17.y, v1, c17.z
dp4 o0.z, c2, r0
dp3 r1.x, c4, r2
dp3 r1.y, c5, r2
dp3 r1.z, c6, r2
dp4 o0.w, c3, r0
dp3 r0.w, r1, -c9
add r2.xyz, r0, -c11
mad r0.w, r0.w, c18.x, c18.y
mul r1.xyz, r0.w, c8
mov r0, c15
mad r0, r0, v1.w, c14
mad r0.xyz, c10, r0.w, r0
dp3 r0.w, r2, r2
mad r1.w, v1.w, c16.x, c16.y
rsq r0.w, r0.w
mad o1.xyz, r1, r1.w, r0
rcp r0.w, r0.w
mul r0.xy, c13, v2
mul r0.w, r0.w, c12.w
mul o4.xy, r0, c12
mul r0.w, r0.w, r0.w
mov o3.xy, r0
min r0.w, r0.w, c17.x
add o1.w, -r0.w, c17.x
mul o2, r0.w, c17.w
// approximately 33 instruction slots used