add game&rawdata
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174
gamedata/shaders/r2/test/p2b_accum_sun_far.ps.log
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174
gamedata/shaders/r2/test/p2b_accum_sun_far.ps.log
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--------------------------------------------------------------------------------
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Running performance on file test\p2B_accum_sun_far.ps
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-------------------- NV40 --------------------
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Target: GeForce 6800 Ultra (NV40) :: Unified Compiler: v65.04
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IPU0 ------ Simplified schedule: --------
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Pass | Unit | uOp | PC: Op
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-----+--------+------+-------------------------
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1 | SCT0 | div | 0: TEXr r0, f[TEX0], TEX1;
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| TEX | tex | 0: TEXr r0, f[TEX0], TEX1;
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| SCB0 | mov | 1: MOVr r3.xyz, r0;
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| SCB1 | mov | 2: MOVr r3.w, const.---x;
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| | |
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2 | SCB0 | dp4 | 4: DP4r r1.x, const, r3;
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| SCB1 | nop | 4: DP4r r1.x, const, r3;
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| | |
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3 | SCT1 | div | 6: RCPr r1.y, r1;
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| SCB0 | dp4 | 7: DP4r r2.z, const, r3;
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| SCB1 | nop | 7: DP4r r2.z, const, r3;
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| | |
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4 | SCB0 | dp4 | 9: DP4r r2.w, const, r3;
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| SCB1 | nop | 9: DP4r r2.w, const, r3;
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| | |
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5 | SCB0 | mad | 13: MADr r2.xy, r2.zw--, r1.yy--, const.xy--;
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| SCB1 | mad | 11: MADr r1.zw, r2, r1.--yy, const.--xx;
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| | |
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6 | SCT0 | mov | 15: TEXr r1.x, r1.zwzz, TEX0;
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| TEX | tex | 15: TEXr r1.x, r1.zwzz, TEX0;
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| SCB1 | mad | 16: MADr r1.zw, r2, r1.--yy, const.--xy;
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| | |
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7 | SCT0 | mov | 18: TEXr r4.x, r1.zwzz, TEX0;
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| TEX | tex | 18: TEXr r4.x, r1.zwzz, TEX0;
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| SCB0 | dp4 | 19: DP4r r1.z, const, r3;
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| SCB1 | nop | 19: DP4r r1.z, const, r3;
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| | |
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8 | SCT0 | mov | 21: TEXr r2.x, r2, TEX0;
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| TEX | tex | 21: TEXr r2.x, r2, TEX0;
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| SCB0 | dp4 | 22: DP4r r1.w, const, r3;
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| SCB1 | nop | 22: DP4r r1.w, const, r3;
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| | |
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9 | SCB0 | dp4 | 24: DP4r r4.z, const, r3;
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| SCB1 | nop | 24: DP4r r4.z, const, r3;
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| | |
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10 | SCT1 | mov | 26: MOVr r3.z, r0.--w-;
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| SCB0 | add | 27: ADDr h6.y,-r4.-x--, r4.-z--;
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| SCB1 | add | 28: ADDr h6.w,-r1.---x, r4.---z;
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11 | SCT0 | mov | 29: TEXh h1.w, r1.zwzz, TEX3;
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| TEX | tex | 29: TEXh h1.w, r1.zwzz, TEX3;
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| SCB0 | dp3 | 30: DP3h h4.z, r0, r0;
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| | |
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12 | SCB0 | mad | 31: MADr r4.xy, r2.zw--, r1.yy--, const.xx--;
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| SCB1 | lg2 | 33: LG2h/2 h4.w, |h4.zzzz|;
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| | |
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13 | SCB0 | add | 35: ADDr h6.z,-r2.--x-, r4;
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| SCB1 | ex2 | 34: EX2h h4.w,-h4.wwww;
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| | |
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14 | SCT0 | mov | 36: TEXr r1.x, r4, TEX0;
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| TEX | tex | 36: TEXr r1.x, r4, TEX0;
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| SCB0 | add | 37: ADDr h6.x,-r1, r4.z---;
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15 | SCT0 | div | 38: TEXh h4.xyz, f[TEX0], TEX2;
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| TEX | tex | 38: TEXh h4.xyz, f[TEX0], TEX2;
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| SCB0/1 | mul | 39: MOVrc0 hc,-h6;
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| | |
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16 | SCT0 | mul | 40: MULr r1.xy, r4, const.xx--;
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| SCB0 | dp3 | 42: DP3h r3.x,-const, h4;
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| | |
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17 | SCB0 | frc | 44: FRCr h5.xy, r1;
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18 | SCT0/1 | mul | 45: MOVh h2, const.xxxx;
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| SCB0 | mad | 47: MADh h0.xyz, r0,-h4.www-,-const;
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19 | SCT1 | mov | 49: NRMh h0.xyz, h0;
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| SRB | nrm | 49: NRMh h0.xyz, h0;
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| SCB0 | dp3 | 50: DP3h r3.y, h0, h4;
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| | |
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20 | SCT0/1 | mul | 51: MOVh h2(LT0.xyzw), const.xxxx;
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| SCB1 | add | 53: ADDh h5.zw,-h5.--xy, const.--xx;
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21 | SCT0 | mul | 56: MULh h4.yz, h5.-yx-, h5.-zw-;
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| SCT1 | mul | 55: MULh h4.w, h5.---y, h5.---x;
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| SCB0 | mul | 57: MULh h4.x, h5.w---, h5.z---;
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| SCB1 | mul | 58: MULr_s r2.w, r0.---z, const.---x;
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22 | SCB0 | dp4 | 60: DP4h h1.z, h2, h4;
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| SCB1 | nop | 60: DP4h h1.z, h2, h4;
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23 | SCT0 | mul | 61: MULr r2.x, r2.w---, r2.w---;
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| SCB1 | mad | 62: MADh h4.w, h1,-h1.---z, const.---x;
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24 | SCT0 | mul | 64: MULr h1.x, h4.w---, r2;
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| SCB0 | mad | 65: MADh h2.x, h1.w---, h1.z---, h1;
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25 | SCT0 | mov | 66: TEXh h0, r3, TEX4;
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| TEX | tex | 66: TEXh h0, r3, TEX4;
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| SCB0/1 | mul | 67: MULh h0, h0, const;
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26 | SCT0 | div | 69: TEXh h1, f[TEX0], TEX5;
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| TEX | tex | 69: TEXh h1, f[TEX0], TEX5;
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| SCB0/1 | mad | 70: MADh h0, h0, h2.xxxx, h1;
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Pass SCT TEX SCB
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1: 50% 100% 100%
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2: 0% 0% 100%
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3: 25% 0% 100%
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4: 0% 0% 100%
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5: 0% 0% 100%
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6: 0% 100% 50%
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7: 0% 100% 100%
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8: 0% 100% 100%
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9: 0% 0% 100%
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10: 25% 0% 50%
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11: 0% 100% 75%
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12: 0% 0% 75%
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13: 0% 0% 50%
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14: 0% 100% 25%
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15: 50% 100% 100%
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16: 50% 0% 75%
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17: 0% 0% 50%
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18: 100% 0% 75%
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19: 0% 0% 75%
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20: 100% 0% 50%
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21: 75% 0% 50%
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22: 0% 0% 100%
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23: 25% 0% 25%
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24: 25% 0% 25%
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25: 0% 100% 100%
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26: 50% 100% 100%
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MEAN: 22% 34% 75%
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Pass SCT0 SCT1 TEX SCB0 SCB1
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1: 100% 0% 100% 100% 100%
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2: 0% 0% 0% 100% 100%
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3: 0% 100% 0% 100% 100%
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4: 0% 0% 0% 100% 100%
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5: 0% 0% 0% 100% 100%
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6: 0% 0% 100% 0% 100%
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7: 0% 0% 100% 100% 100%
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8: 0% 0% 100% 100% 100%
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9: 0% 0% 0% 100% 100%
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10: 0% 100% 0% 100% 100%
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11: 0% 0% 100% 100% 0%
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12: 0% 0% 0% 100% 100%
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13: 0% 0% 0% 100% 100%
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14: 0% 0% 100% 100% 0%
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15: 100% 0% 100% 100% 100%
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16: 100% 0% 0% 100% 0%
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17: 0% 0% 0% 100% 0%
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18: 100% 100% 0% 100% 0%
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19: 0% 0% 0% 100% 0%
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20: 100% 100% 0% 0% 100%
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21: 100% 100% 0% 100% 100%
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22: 0% 0% 0% 100% 100%
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23: 100% 0% 0% 0% 100%
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24: 100% 0% 0% 100% 0%
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25: 0% 0% 100% 100% 100%
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26: 100% 0% 100% 100% 100%
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MEAN: 34% 19% 34% 88% 73%
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Cycles: 28.25 :: R Regs Used: 5 :: R Regs Max Index (0 based): 4
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--------------------------------------------------------------------------------
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Running performance on file test\p2b_accum_sun_far.ps
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-------------------- NV40 --------------------
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Target: GeForce 6800 Ultra (NV40) :: Unified Compiler: v81.95
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Cycles: 23.00 :: R Regs Used: 4 :: R Regs Max Index (0 based): 3
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Pixel throughput (assuming 1 cycle texture lookup) 278.26 MP/s
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--------------------------------------------------------------------------------
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Running performance on file test\p2b_accum_sun_far.ps
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-------------------- G70 --------------------
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Target: GeForce 7800 GT (G70) :: Unified Compiler: v81.95
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Cycles: 21.00 :: R Regs Used: 4 :: R Regs Max Index (0 based): 3
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Pixel throughput (assuming 1 cycle texture lookup) 457.14 MP/s
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