-------------------------------------------------------------------------------- Running performance on file test\p30_deffer_impl_flat_d.ps -------------------- NV40 -------------------- Target: GeForce 6800 Ultra (NV40) :: Unified Compiler: v65.04 IPU0 ------ Simplified schedule: -------- Pass | Unit | uOp | PC: Op -----+--------+------+------------------------- 1 | SCT0 | div | 2: TEXh h0, f[TEX1], TEX1; | SCT1 | mul | 0: MOVh h6.w, const.---x; | TEX | tex | 2: TEXh h0, f[TEX1], TEX1; | SCB0 | dp4 | 3: DP4h h1.x, h0, const.xxxx; | SCB1 | nop | 3: DP4h h1.x, h0, const.xxxx; | | | 2 | SCT0/1 | div | 5: DIVh h1, h0, h1; | | | 3 | SCT0 | div | 6: TEXh h0.yzw, f[TEX6], TEX6; | TEX | tex | 6: TEXh h0.yzw, f[TEX6], TEX6; | SCB0 | add | 7: ADDh h2.xyz, h0.wzy-, const.xxx-; | | | 4 | SCT0 | div | 9: TEXh h0.yzw, f[TEX6], TEX7; | TEX | tex | 9: TEXh h0.yzw, f[TEX6], TEX7; | SCB0 | add | 10: ADDh h0.xyz, h0.wzy-, const.xxx-; | | | 5 | SCT0 | mul | 12: MULh h0.xyz, h1.yyy-, h0; | SCB0 | mad | 13: MADh h4.xyz, h2, h1.xxx-, h0; | | | 6 | SCT0 | div | 14: TEXh h0.yzw, f[TEX6], TEX9; | TEX | tex | 14: TEXh h0.yzw, f[TEX6], TEX9; | SCB0 | add | 15: ADDh h2.xyz, h0.wzy-, const.xxx-; | | | 7 | SCT0 | div | 17: TEXh h0.yzw, f[TEX6], TEX8; | TEX | tex | 17: TEXh h0.yzw, f[TEX6], TEX8; | SCB0 | add | 18: ADDh h3.xyz, h0.wzy-, const.xxx-; | SCB1 | mul | 20: MOVh h0.w, const; | | | 8 | SCT0 | mul | 22: MADh h3.xyz, h3, h1.zzz-, h4; | SCB0 | mad | 22: MADh h3.xyz, h3, h1.zzz-, h4; | | | 9 | SCT0 | div | 23: TEXh h0.xyz, f[TEX6], TEX3; | TEX | tex | 23: TEXh h0.xyz, f[TEX6], TEX3; | SCB0 | mul | 24: MULh h4.xyz, h0, h1.yyy-; | | | 10 | SCT0 | div | 25: TEXh h6.xyz, f[TEX6], TEX5; | TEX | tex | 25: TEXh h6.xyz, f[TEX6], TEX5; | SCB0 | mad | 26: MADh h0.xyz, h2, h1.www-, h3; | | | 11 | SCT0 | div | 27: TEXh h2.xyz, f[TEX6], TEX2; | TEX | tex | 27: TEXh h2.xyz, f[TEX6], TEX2; | SCB0 | mad | 28: MADh h3.xyz, h2, h1.xxx-, h4; | | | 12 | SCT0 | div | 29: TEXh h2.xyz, f[TEX6], TEX4; | TEX | tex | 29: TEXh h2.xyz, f[TEX6], TEX4; | SCB0 | mad | 30: MADh h1.xyz, h2, h1.zzz-, h3; | | | 13 | SCT0 | mul | 31: MOVh h3.xy, h0; | SCT1 | mul | 32: MOVh/2 h3.z, h0; | SCB0 | mad | 33: MADh h6.xyz, h6, h1.www-, h1; | | | 14 | SCT0 | div | 34: TEXh h2, f[TEX1], TEX0; | TEX | tex | 34: TEXh h2, f[TEX1], TEX0; | SCB0 | mul | 35: MULh h4.xyz, h0, const.xxy-; | SCB1 | mul | 37: MOVh h4.w, h2; | | | 15 | SCT0 | div | 38: DP3h h0.x, f[TEX3], h3; | SCB0 | dp3 | 38: DP3h h0.x, f[TEX3], h3; | | | 16 | SCT0 | div | 39: DP3h h0.y, f[TEX4], h4; | SCB0 | dp3 | 39: DP3h h0.y, f[TEX4], h4; | | | 17 | SCT0 | div | 40: DP3h h0.z, f[TEX5], h4; | SCB0 | dp3 | 40: DP3h h0.z, f[TEX5], h4; | | | 18 | SCT1 | mov | 41: NRMh h4.xyz, h0; | SRB | nrm | 41: NRMh h4.xyz, h0; | SCB0 | mul | 42: MULh*2 h6.xyz, h6, h2; | | | 19 | SCT0 | div | 43: MADh h0.xyz, h4, const.xxx-, f[TEX2]; | SCB0 | mad | 43: MADh h0.xyz, h4, const.xxx-, f[TEX2]; Pass SCT TEX SCB 1: 75% 100% 100% 2: 100% 0% 0% 3: 50% 100% 75% 4: 50% 100% 75% 5: 75% 0% 75% 6: 50% 100% 75% 7: 50% 100% 100% 8: 75% 0% 75% 9: 50% 100% 75% 10: 50% 100% 75% 11: 50% 100% 75% 12: 50% 100% 75% 13: 75% 0% 75% 14: 50% 100% 100% 15: 75% 0% 75% 16: 75% 0% 75% 17: 75% 0% 75% 18: 0% 0% 75% 19: 75% 0% 75% 20: 0% 0% 0% MEAN: 57% 50% 71% Pass SCT0 SCT1 TEX SCB0 SCB1 1: 100% 100% 100% 100% 100% 2: 100% 100% 0% 0% 0% 3: 100% 0% 100% 100% 0% 4: 100% 0% 100% 100% 0% 5: 100% 0% 0% 100% 0% 6: 100% 0% 100% 100% 0% 7: 100% 0% 100% 100% 100% 8: 100% 0% 0% 100% 0% 9: 100% 0% 100% 100% 0% 10: 100% 0% 100% 100% 0% 11: 100% 0% 100% 100% 0% 12: 100% 0% 100% 100% 0% 13: 100% 100% 0% 100% 0% 14: 100% 0% 100% 100% 100% 15: 100% 0% 0% 100% 0% 16: 100% 0% 0% 100% 0% 17: 100% 0% 0% 100% 0% 18: 0% 0% 0% 100% 0% 19: 100% 0% 0% 100% 0% 20: 0% 0% 0% 0% 0% MEAN: 90% 15% 50% 90% 15% Cycles: 20.00 :: R Regs Used: 4 :: R Regs Max Index (0 based): 3 -------------------------------------------------------------------------------- Running performance on file test\p30_deffer_impl_flat_d.ps -------------------- NV40 -------------------- Target: GeForce 6800 Ultra (NV40) :: Unified Compiler: v81.95 Cycles: 19.00 :: R Regs Used: 4 :: R Regs Max Index (0 based): 3 Pixel throughput (assuming 1 cycle texture lookup) 336.84 MP/s -------------------------------------------------------------------------------- Running performance on file test\p30_deffer_impl_flat_d.ps -------------------- G70 -------------------- Target: GeForce 7800 GT (G70) :: Unified Compiler: v81.95 Cycles: 18.00 :: R Regs Used: 4 :: R Regs Max Index (0 based): 3 Pixel throughput (assuming 1 cycle texture lookup) 533.33 MP/s