360 lines
14 KiB
Text
360 lines
14 KiB
Text
--------------------------------------------------------------------------------
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Running performance on file test\p30_accum_sun_near.ps
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-------------------- NV40 --------------------
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Target: GeForce 6800 Ultra (NV40) :: Unified Compiler: v65.04
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IPU0 ------ Simplified schedule: --------
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Pass | Unit | uOp | PC: Op
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-----+--------+------+-------------------------
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1 | SCT0 | div | 0: TEXr r0, f[TEX0], TEX0;
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| TEX | tex | 0: TEXr r0, f[TEX0], TEX0;
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| SCB0/1 | mad | 1: MADr r1, r0.xyzx, const.xxxy, const.yyyx;
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| | |
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2 | SCT1 | mov | 3: NRMh h0.xyz, r0;
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| SRB | nrm | 3: NRMh h0.xyz, r0;
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| SCB0 | dp4 | 4: DP4r r2.x, const, r1;
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| SCB1 | nop | 4: DP4r r2.x, const, r1;
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3 | SCB0 | dp4 | 6: DP4r r4.x, const, r1;
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| SCB1 | nop | 6: DP4r r4.x, const, r1;
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4 | SCB0 | dp4 | 8: DP4r r4.y, const, r1;
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| SCB1 | nop | 8: DP4r r4.y, const, r1;
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5 | SCT1 | div | 10: RCPr r6.z, r2;
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| SCB0 | dp4 | 11: DP4r r6.y, const, r1;
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| SCB1 | nop | 11: DP4r r6.y, const, r1;
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6 | SCB0 | mad | 13: MADr r2.xy, r4, r6.zz--, const.xy--;
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| SCB1 | mad | 15: MADr r4.zw, r4.--xy, r6.--zz, const.--yx;
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8 | SCT0 | mov | 17: TEXr r6.x, r2, TEX2;
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| TEX | tex | 17: TEXr r6.x, r2, TEX2;
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| SCB0 | add | 18: ADDr h6.y, r6,-r6.-x--;
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| SCB1 | mad | 19: MADr r3.zw, r4.--xy, r6.--zz, const.--xx;
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9 | SCT0 | mov | 21: TEXr r2.x, r4.zwzz, TEX2;
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| TEX | tex | 21: TEXr r2.x, r4.zwzz, TEX2;
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| SCB1 | mad | 22: MADr r2.zw, r4.--xy, r6.--zz, const.--xx;
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10 | SCB1 | add | 24: ADDr h6.z, r6.--y-,-r2.--x-;
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11 | SCT0 | mov | 25: TEXr r2.x, r2.zwzz, TEX2;
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| TEX | tex | 25: TEXr r2.x, r2.zwzz, TEX2;
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| SCB1 | add | 26: ADDr h6.w, r6.---y,-r2.---x;
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12 | SCT0 | mov | 27: TEXr r2.x, r3.zwzz, TEX2;
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| TEX | tex | 27: TEXr r2.x, r3.zwzz, TEX2;
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| SCB0 | add | 28: ADDr h6.x, r6.y---,-r2;
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13 | SCT0/1 | mul | 29: MOVrc0 hc,-h6;
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| SCB1 | mad | 30: MADr r4.zw, r4.--xy, r6.--zz, const.--xy;
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14 | SCT0 | mov | 32: TEXr r3.x, r4.zwzz, TEX2;
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| TEX | tex | 32: TEXr r3.x, r4.zwzz, TEX2;
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| SCB1 | mad | 33: MADr r4.zw, r4.--xy, r6.--zz, const.--xy;
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15 | SCT0/1 | mul | 35: MOVh h4, const.xxxx;
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| SCB0 | add | 37: ADDr h5.y, r6,-r3.-x--;
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16 | SCT0/1 | mul | 38: MOVh h4(LT0.xyzw), const.xxxx;
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| SCB1 | mad | 40: MADr r5.zw, r4.--xy, r6.--zz, const.--xy;
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17 | SCT0 | mov | 42: TEXr r3.x, r4.zwzz, TEX2;
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| TEX | tex | 42: TEXr r3.x, r4.zwzz, TEX2;
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| SCB1 | mad | 43: MADr r4.zw, r4.--xy, r6.--zz, const.--xy;
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18 | SCB1 | add | 45: ADDr h5.z, r6.--y-,-r3.--x-;
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19 | SCB0/1 | mad | 46: MADr r6.xw, r4.x--y, r6.z--z, const.x--y;
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20 | SCT0 | mov | 48: TEXr r3.x, r4.zwzz, TEX2;
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| TEX | tex | 48: TEXr r3.x, r4.zwzz, TEX2;
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| SCB1 | add | 49: ADDr h5.w, r6.---y,-r3.---x;
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21 | SCT0 | mov | 50: TEXr r6.x, r6.xwyy, TEX2;
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| TEX | tex | 50: TEXr r6.x, r6.xwyy, TEX2;
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| SCB1 | mad | 51: MADr r4.zw, r4.--xy, r6.--zz, const.--xy;
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22 | SCT0 | mov | 53: TEXr r3.x, r4.zwzz, TEX2;
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| TEX | tex | 53: TEXr r3.x, r4.zwzz, TEX2;
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| SCB0 | add | 54: ADDr h5.x, r6.y---,-r3;
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23 | SCT0/1 | mul | 55: MOVrc0 hc,-h5;
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| SCB0 | mad | 56: MADr r3.xy, r4, r6.zz--, const.xy--;
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24 | SCT0/1 | mul | 58: MOVh h5, const.xxxx;
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| SCB0/1 | mul | 60: MOVh h5(LT0.xyzw), const.xxxx;
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25 | SCT0 | mov | 62: TEXr r3.x, r3, TEX2;
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| TEX | tex | 62: TEXr r3.x, r3, TEX2;
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| SCB0 | add | 63: ADDr h6.y, r6,-r3.-x--;
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26 | SCT0 | mov | 64: TEXr r5.x, r5.zwzz, TEX2;
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| TEX | tex | 64: TEXr r5.x, r5.zwzz, TEX2;
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| SCB1 | mad | 65: MADr r5.zw, r4.--xy, r6.--zz, const.--xy;
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27 | SCB1 | add | 67: ADDr h6.z, r6.--y-,-r5.--x-;
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28 | SCT0 | mov | 68: TEXr r5.x, r5.zwzz, TEX2;
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| TEX | tex | 68: TEXr r5.x, r5.zwzz, TEX2;
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| SCB1 | mad | 69: MADr r5.zw, r4.--xy, r6.--zz, const.--xy;
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29 | SCB1 | add | 71: ADDr h6.w, r6.---y,-r5.---x;
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30 | SCT0 | mov | 72: TEXr r5.x, r5.zwzz, TEX2;
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| TEX | tex | 72: TEXr r5.x, r5.zwzz, TEX2;
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| SCB0 | add | 73: ADDr h6.x, r6.y---,-r5;
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31 | SCT0/1 | mul | 74: MOVrc0 hc,-h6;
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| SCB0 | mad | 75: MADr r5.xy, r4, r6.zz--, const.xy--;
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32 | SCT0/1 | mul | 77: MOVh h6, const.xxxx;
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| SCB0/1 | mul | 79: MOVh h6(LT0.xyzw), const.xxxx;
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33 | SCT0 | mov | 81: TEXr r5.x, r5, TEX2;
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| TEX | tex | 81: TEXr r5.x, r5, TEX2;
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| SCB0 | add | 83: ADDr h10.y,-r5.-x--, r6;
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| SCB1 | add | 82: ADDr h10.z, r6.--y-,-r6.--x-;
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34 | SCB0/1 | mad | 84: MADr r6.xw, r4.x--y, r6.z--z, const.x--x;
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35 | SCT0 | mov | 86: TEXr r6.x, r6.xwzz, TEX2;
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| TEX | tex | 86: TEXr r6.x, r6.xwzz, TEX2;
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| SCB1 | mad | 87: MADr r6.zw, r4.--xy, r6.--zz, const.--xx;
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36 | SCT0 | mov | 89: TEXr r4.x, r6.zwzz, TEX2;
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| TEX | tex | 89: TEXr r4.x, r6.zwzz, TEX2;
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| SCB0 | add | 90: ADDr h10.x, r6.y---,-r4;
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| SCB1 | add | 91: ADDr h10.w, r6.---y,-r6.---x;
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37 | SCT0/1 | mul | 92: MOVrc0 hc,-h10;
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| SCB0 | mul | 93: MULr r5.xy, r6.zw--, const.xx--;
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38 | SCT0/1 | mul | 95: MOVh h8, const.xxxx;
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| SCB0 | frc | 97: FRCr h10.xy, r5;
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39 | SCT1 | mul | 98: MULh h10.w, h10.---y, h10.---x;
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| SCB0 | add | 99: ADDh h12.xy,-h10, const.xx--;
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40 | SCT0 | mul | 101: MULh h10.yz, h10.-yx-, h12.-xy-;
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| SCB0/1 | mul | 102: MOVh h8(LT0.xyzw), const.xxxx;
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41 | SCT0 | mul | 104: MULh h10.x, h12.y---, h12;
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| SCB0 | dp4 | 105: DP4h h8.x, h8, h10;
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| SCB1 | nop | 105: DP4h h8.x, h8, h10;
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42 | SCT0 | mul | 106: MULr r5.xy, r5.zw--, const.xx--;
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| SCB0 | frc | 108: FRCr h10.xy, r5;
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43 | SCT1 | mul | 109: MULh h10.w, h10.---y, h10.---x;
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| SCB1 | add | 110: ADDh h8.zw,-h10.--xy, const.--xx;
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44 | SCT0 | mul | 112: MULh h10.yz, h10.-yx-, h8.-zw-;
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| SCB0 | mul | 113: MULh h10.x, h8.w---, h8.z---;
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45 | SCB0 | dp4 | 114: DP4h h8.y, h6, h10;
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| SCB1 | nop | 114: DP4h h8.y, h6, h10;
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46 | SCB0 | mul | 115: MULr r3.xy, r4.zw--, const.xx--;
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47 | SCB0 | frc | 117: FRCr h6.xy, r3;
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48 | SCT1 | mul | 118: MULh h6.w, h6.---y, h6.---x;
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| SCB1 | add | 119: ADDh h8.zw,-h6.--xy, const.--xx;
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49 | SCT0 | mul | 121: MULh h6.yz, h6.-yx-, h8.-zw-;
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| SCB0 | mul | 122: MULh h6.x, h8.w---, h8.z---;
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50 | SCB0 | dp4 | 123: DP4h h8.z, h5, h6;
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| SCB1 | nop | 123: DP4h h8.z, h5, h6;
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51 | SCT1 | mul | 124: MULr r2.zw, r3, const.--xx;
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| SCB0 | frc | 126: FRCr h5.xy, r2.zw--;
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| SCB1 | mov | 127: MOVr r3.z, r0.--w-;
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52 | SCT1 | mul | 128: MULh h5.w, h5.---y, h5.---x;
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| SCB0 | add | 129: ADDh h6.xy,-h5, const.xx--;
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53 | SCT0 | mul | 131: MULh h5.yz, h5.-yx-, h6.-xy-;
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| SCB0 | mul | 132: MULh h5.x, h6.y---, h6;
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54 | SCB0 | dp4 | 133: DP4h h8.w, h4, h5;
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| SCB1 | nop | 133: DP4h h8.w, h4, h5;
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55 | SCT0 | div | 134: TEXh h4.xyz, f[TEX0], TEX1;
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| TEX | tex | 134: TEXh h4.xyz, f[TEX0], TEX1;
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| SCB0 | dp3 | 135: DP3h*2 h0.w, h0, h4;
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56 | SCB0 | mad | 136: MADh h0.xyz, h4,-h0.www-, h0;
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57 | SCB0 | dp4 | 137: DP4r r2.z, const, r1;
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| SCB1 | nop | 137: DP4r r2.z, const, r1;
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58 | SCB0 | dp4 | 139: DP4r r2.w, const, r1;
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| SCB1 | nop | 139: DP4r r2.w, const, r1;
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59 | SCT0 | mov | 141: TEXh h0.w, r2.zwzz, TEX3;
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| TEX | tex | 141: TEXh h0.w, r2.zwzz, TEX3;
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| SCB0 | dp4 | 142: DP4h h4.w, h8, const.xxxx;
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| SCB1 | nop | 142: DP4h h4.w, h8, const.xxxx;
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60 | SCB0 | dp3 | 144: DP3h r3.x,-const, h4;
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| SCB1 | mul | 146: MULh h2.w, h4, h0;
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61 | SCB0 | dp3 | 147: DP3h r3.y,-const, h0;
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62 | SCT0 | mov | 149: TEXh h1, r3, TEX4;
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| TEX | tex | 149: TEXh h1, r3, TEX4;
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| SCB0/1 | mul | 150: MULh h1, h1, const;
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63 | SCT0 | div | 152: TEXh h0, f[TEX0], TEX5;
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| TEX | tex | 152: TEXh h0, f[TEX0], TEX5;
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| SCB0/1 | mad | 153: MADh h0, h1, h2.wwww, h0;
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Pass SCT TEX SCB
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1: 50% 100% 100%
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2: 0% 0% 100%
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3: 0% 0% 100%
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4: 0% 0% 100%
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5: 25% 0% 100%
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6: 0% 0% 100%
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7: 0% 0% 0%
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8: 0% 100% 75%
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9: 0% 100% 50%
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10: 0% 0% 25%
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11: 0% 100% 25%
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12: 0% 100% 25%
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13: 100% 0% 50%
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14: 0% 100% 50%
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15: 100% 0% 25%
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16: 100% 0% 50%
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17: 0% 100% 50%
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18: 0% 0% 25%
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19: 0% 0% 50%
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20: 0% 100% 25%
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21: 0% 100% 50%
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22: 0% 100% 25%
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23: 100% 0% 50%
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24: 100% 0% 100%
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25: 0% 100% 25%
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26: 0% 100% 50%
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27: 0% 0% 25%
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28: 0% 100% 50%
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29: 0% 0% 25%
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30: 0% 100% 25%
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31: 100% 0% 50%
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32: 100% 0% 100%
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33: 0% 100% 50%
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34: 0% 0% 50%
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35: 0% 100% 50%
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36: 0% 100% 50%
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37: 100% 0% 50%
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38: 100% 0% 50%
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39: 25% 0% 50%
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40: 50% 0% 100%
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41: 25% 0% 100%
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42: 50% 0% 50%
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43: 25% 0% 50%
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44: 50% 0% 25%
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45: 0% 0% 100%
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46: 0% 0% 50%
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47: 0% 0% 50%
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48: 25% 0% 50%
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49: 50% 0% 25%
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50: 0% 0% 100%
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51: 50% 0% 75%
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52: 25% 0% 50%
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53: 50% 0% 25%
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54: 0% 0% 100%
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55: 50% 100% 75%
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56: 0% 0% 75%
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57: 0% 0% 100%
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58: 0% 0% 100%
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59: 0% 100% 100%
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60: 0% 0% 75%
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61: 0% 0% 75%
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62: 0% 100% 100%
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63: 50% 100% 100%
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MEAN: 23% 33% 60%
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Pass SCT0 SCT1 TEX SCB0 SCB1
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1: 100% 0% 100% 100% 100%
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2: 0% 0% 0% 100% 100%
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3: 0% 0% 0% 100% 100%
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4: 0% 0% 0% 100% 100%
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5: 0% 100% 0% 100% 100%
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6: 0% 0% 0% 100% 100%
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7: 0% 0% 0% 0% 0%
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8: 0% 0% 100% 100% 100%
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9: 0% 0% 100% 0% 100%
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10: 0% 0% 0% 0% 100%
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11: 0% 0% 100% 0% 100%
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12: 0% 0% 100% 100% 0%
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13: 100% 100% 0% 0% 100%
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14: 0% 0% 100% 0% 100%
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15: 100% 100% 0% 100% 0%
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16: 100% 100% 0% 0% 100%
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17: 0% 0% 100% 0% 100%
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18: 0% 0% 0% 0% 100%
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19: 0% 0% 0% 100% 100%
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20: 0% 0% 100% 0% 100%
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21: 0% 0% 100% 0% 100%
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22: 0% 0% 100% 100% 0%
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23: 100% 100% 0% 100% 0%
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24: 100% 100% 0% 100% 100%
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25: 0% 0% 100% 100% 0%
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26: 0% 0% 100% 0% 100%
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27: 0% 0% 0% 0% 100%
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28: 0% 0% 100% 0% 100%
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29: 0% 0% 0% 0% 100%
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30: 0% 0% 100% 100% 0%
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31: 100% 100% 0% 100% 0%
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32: 100% 100% 0% 100% 100%
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33: 0% 0% 100% 100% 100%
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34: 0% 0% 0% 100% 100%
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35: 0% 0% 100% 0% 100%
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36: 0% 0% 100% 100% 100%
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37: 100% 100% 0% 100% 0%
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38: 100% 100% 0% 100% 0%
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39: 0% 100% 0% 100% 0%
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40: 100% 0% 0% 100% 100%
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41: 100% 0% 0% 100% 100%
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42: 100% 0% 0% 100% 0%
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43: 0% 100% 0% 0% 100%
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44: 100% 0% 0% 100% 0%
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45: 0% 0% 0% 100% 100%
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46: 0% 0% 0% 100% 0%
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47: 0% 0% 0% 100% 0%
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48: 0% 100% 0% 0% 100%
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49: 100% 0% 0% 100% 0%
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50: 0% 0% 0% 100% 100%
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51: 0% 100% 0% 100% 100%
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52: 0% 100% 0% 100% 0%
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53: 100% 0% 0% 100% 0%
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54: 0% 0% 0% 100% 100%
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55: 100% 0% 100% 100% 0%
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56: 0% 0% 0% 100% 0%
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57: 0% 0% 0% 100% 100%
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58: 0% 0% 0% 100% 100%
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59: 0% 0% 100% 100% 100%
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60: 0% 0% 0% 100% 0%
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61: 0% 0% 0% 100% 0%
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62: 0% 0% 100% 100% 100%
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63: 100% 0% 100% 100% 100%
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MEAN: 28% 23% 33% 71% 65%
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Cycles: 78.75 :: R Regs Used: 7 :: R Regs Max Index (0 based): 6
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--------------------------------------------------------------------------------
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Running performance on file test\p30_accum_sun_near.ps
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-------------------- NV40 --------------------
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Target: GeForce 6800 Ultra (NV40) :: Unified Compiler: v81.95
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Cycles: 58.25 :: R Regs Used: 5 :: R Regs Max Index (0 based): 4
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Pixel throughput (assuming 1 cycle texture lookup) 110.34 MP/s
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--------------------------------------------------------------------------------
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Running performance on file test\p30_accum_sun_near.ps
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-------------------- G70 --------------------
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Target: GeForce 7800 GT (G70) :: Unified Compiler: v81.95
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Cycles: 50.00 :: R Regs Used: 4 :: R Regs Max Index (0 based): 3
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Pixel throughput (assuming 1 cycle texture lookup) 192.00 MP/s
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